Two students walk into the same classroom on day one. One is from a Tier-1 college, has written Verilog in three lab courses, and has already taped out a small design in a university project. The other is from a Tier-3 college where the VLSI lab has four working machines and no EDA licence — bright, motivated, and has never written a line of Verilog in her life.
Most training programs put both of them on page one of the same chapter and start teaching.
Within two weeks, one is bored and the other is drowning. By the end of the first month, the second student has quietly concluded that she isn't cut out for chip design. She is wrong — but nothing in how the course was structured gave her a chance to find that out.
The gap is not what people say it is
It's convenient to say "colleges don't teach industry tools." It's also too simple, and not quite true. The real picture is layered, and the layers matter.
Tier-1 colleges
Often build genuinely strong fundamentals. What's missing is industry exposure — a student can explain CMOS inverter behaviour from first principles and have never opened a production EDA tool. The theory is solid; the hands are untrained.
Tier-2 and Tier-3 colleges
Frequently lack both. Not because the students are weaker, but because the labs, the licences and the faculty exposure aren't there. Capable people graduate with no route into the industry — not for want of ability, but because nobody ever showed them what the industry expects.
Across every tier
Mentorship is close to non-existent. A student stuck on a concept at midnight has nowhere to turn — not a senior, not a professor, not a forum that actually answers. That silence is where most people quit.
So when a batch assembles, you are not looking at one gap. You are looking at several different gaps wearing the same uniform.
Why a common starting point fails everyone
Here is the uncomfortable arithmetic. If you pitch the first module at the strongest student in the room, you lose a third of the batch in the first fortnight. If you pitch it at the weakest, the strongest students disengage — and disengaged students don't come back mentally even when they keep attending.
Most programs resolve this by pitching somewhere in the middle and hoping. The result is a course that is slightly too fast for some and slightly too slow for others, and properly right for almost nobody.
Level Zero exists so that the starting line is actually a line.
What Level Zero actually is
It is a set of pre-recorded modules covering the fundamentals every VLSI engineer is assumed to already have — digital basics, semiconductor theory, CMOS behaviour, an introduction to Verilog, the pieces of network theory and analog electronics that keep resurfacing later. Plus a few advanced topics included purely for reading, so that stronger students have somewhere to go.
It is deliberately not live. Live classes move at one speed. Level Zero is recorded precisely so that each student can move at their own — the student who needs to watch the CMOS module three times can watch it three times, and nobody is watching them do it.
That distinction matters more than it sounds. A remedial class is something you're sent to. An equaliser is something everyone does. There is no separate track, no marked-out group of students who "need extra help." Everyone completes Level Zero. The strong student finishes it quickly and reinforces what they knew loosely. The student from the college with no lab finally gets the foundation she was never given. Both enter Level One on the same footing.
Why it is mandatory
We are occasionally asked to waive it — usually by a student who is confident, and often by one who has genuine reason to be.
We don't waive it, for two reasons.
The first is that confidence and competence diverge more often than people expect. Students who are certain they know CMOS thoroughly routinely find gaps in the Level Zero assessment. Better to find those gaps in week one than in month four, when the same gap is quietly blocking their understanding of something far harder.
The second is that Level One depends on it. If the trainer cannot assume a common baseline, Level One slows down to re-explain fundamentals — and that costs the entire batch. One waived exemption degrades the experience for everyone else in the room.
The part nobody expects
Level Zero is also where the scholarship starts.
10%
Level Zero completion — 5% for finishing the modules, 5% for clearing the assessment.
10%
90% attendance through the program, plus all assignments submitted on time.
20%
Total scholarship available, adjusted against your final instalment.
We don't discount the fee. We reward the behaviour that makes students succeed — preparation, attendance, and submitting work on time. Level Zero is the first place that shows up, and it can be completed before the program even begins.
What actually happens
The honest outcome of Level Zero is not that weak students become strong in three weeks. It's that by the time Level One starts, the trainer can teach one class instead of three, and the student who arrived convinced she was behind has evidence that she isn't.
That second part is worth more than the syllabus. A large share of what stops capable engineers from entering this industry is not knowledge — it is the belief, formed early and rarely questioned, that the people from better colleges are simply better.
Nine of our students — every one of them from a Tier-2 or Tier-3 college, none with prior tapeout experience — designed a processor and fabricated it on GlobalFoundries 180nm silicon in three and a half months. That happened. It started with the same Level Zero everyone else does.
Level Zero is where we take the excuse away. Not the students' excuse — ours. Once every student has the same foundation, we can no longer explain a poor outcome by saying they came in unprepared. That responsibility shifts to us, which is exactly where it belongs.